Photolithographic masks are used to fabricate semiconductor devices such as integrated circuits. The masks are patterned according to the images that are to be printed on, for example, a silicon wafer. Light is transmitted through the openings in the mask and focused onto a photoresist layer that has been coated on the silicon wafer. The transmitted and focused light exposes portions of the photoresist. A developer is used to remove either the exposed portions or the unexposed portions of the resist layer, depending on whether the photoresist is a positive or negative type resist. The remaining photoresist serves to protect the underlying layer during further processing of the wafer (e.g., etching exposed portions of the underlying layer, implanting ions into the wafer, etc.). After the wafer fabrication process for this pattern is performed, the remaining portion of the photoresist layer can be removed from the underlying substrate. The pattern that is printed onto the photoresist correlates with that of the photolithographic mask.
There is a continuing objective to increase the density with which various integrated circuit structures are arranged. As technology nodes decrease, the critical dimension of the features to be printed on the silicon wafer is reduced. As the size of the features becomes smaller than the wavelength of light, distortions occur in the printed patterns. To reduce these distortions, SRAFs are added to the mask between the features to be printed. SRAFs generally are not printed on the semiconductor wafer, but help to balance the optical density of the feature pattern.
SRAFs are placed on a mask in proximity to optical proximity correction (OPC) shapes to assist/improve the photolithography process. In particular, placing SRAFs on a mask improves the process window (PW). It is desirable to use an aggressive SRAF insertion strategy to improve both the imaging quality during photolithography and also the pattern transfer immunity against photolithography process variations. However, a too aggressive insertion strategy may lead to printing and etching of the SRAFs such that the SRAFs can become defects that contribute to random defect generation. This is especially true when a printed SRAF forms a resist line. Moreover, multiple stacked printed SRAFs in integrated levels can form an actual electrical path to signals that can alter (and even destroy) the circuit behavior.
A known approach involves using a second exposure for trimming/removing the printed assist features. For example, in some layers like Poly in 32 nm, 28 nm, and 20 nm technologies, it has been suggested to make the required final design on a gridded pitch, where the resolution enhancement technologies (RET) (illumination/source distribution) are optimized specifically for a particular pitch as illustrated in FIG. 1. In particular, a trim mask 101 is formed on either side of the original design 103, and the trim mask 101 includes printing assist features 105 that are similar in dimension and pitch to the original design 103. Because these technologies use a trim mask 103, assisting features 105 can be printed, as they are then removed later using the trimming phase. While there is proof of the benefit of printing SRAFs with this process, this technique is limited to technologies with a trim mask.
A need therefore exists for a methodology enabling an aggressive SRAF strategy with SRAF printing during the photolithography process, but without the need for a trim mask.